In the electronics industry there is a consistent trend to increase the number of devices that can be formed on a semiconductor wafer. This requires that extremely small line widths be photolithographically printed on the wafer. However, most photolithographic techniques are limited by the degree of flatness of the wafer surface for the depth of focus of projection printers cannot be adjusted to compensate for surface variation which restricts the resolution of the fine line patterns.
The last step in most semiconductor fabrication processes, prior to forming devices on a wafer is to polish the wafer to as high a degree of flatness as possible. The present technique is to place the wafer between a stainless steel, polyurethane coated, holder and a polishing pad. The wafer is tightly held by the polyurethane coating while the holder and the pad are rotated in same direction to polish the wafer. This technique results in variations of surface flatness of approximately eight microns. Such variations result in decreased yields of acceptable devices as the number of devices per unit area increases.
Accordingly, there is a need for a semiconductor wafer polishing technique that can substantially decrease the flatness variations of a semiconductor wafer.